Register now for FREE handson session on VLSI Design using

Title Register now for FREE hands-on session on VLSI Design using Verilog HDL

VLSI Design using Verilog HDL workshop is an amazing opportunity to learn these concepts from Industry perspective to stay ahead in your class and career.

Click here to book your slot elearn.maven-silicon.com/free-vlsi-workshop-freshers or call at 91 98450 16248 | 91 91486 37555.

Limited seats. Hurry up!!

Workshop Topic: VLSI Design using Verilog HDL

Speaker: Mr. P R Sivakumar (CEO-Maven Silicon with 20+ years of experience in Industry and Academia)

Date: Sun, 28/Oct/2018

Time : 9:00 AM to 1:00 PM

Venue : Maven Silicon

Agenda:
Overview of VLSI Design
1. IPs, Chips and SoCs
2. SoC Design
3. ASIC Vs FPGA

RTL Design using Verilog HDL
1. Verilog Language Concepts
2. Verilog language basics and constructs
3. Verilog Abstraction levels
4. Data Types and Operators

Verilog RTL coding Style - Summary
Verilog Labs - Hands on Session
Q & A Session

Take away:
Participation Certificate
Scholarship Coupon

Venue - # 21/1A, III Floor, Marudhar Avenue, Gottigere,, Uttarahalli Hobli, South Taluk, Bannerghatta Road,, Bengaluru, Karnataka 560076