Image processing projects and thesis with matlab and openCV

1. A New VLSI Architecture of Parallel Multiplier Accumulator Based on Radix-2 Modified Booth Algorithm.

2. An Efficient Architecture for 3-D Discrete Wavelet Transform.

3. The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation.

4. Design of On-Chip Bus with OCP Interface.

5. Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix.

6. Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms

7. A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance

8. Single chip encryptor/ decryptor core implementation using AES algoritham

9. Implementation of IEEE 802.11 a WLAN Baseband Processor

10. Design of Simple Spectrum Analyzer

11. A Dual-Purpose Real/Complex Logarithmic Number System ALU

12. An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform.

13. Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers

14. A Spurious-Power Suppression Technique for Multimedia/DSP Applications

15. DDR3 based lookup circuit for high-performance network processing.

16. Multiplication Acceleration Through Twin Precision

17. A Parallel Pipelined Algorithm for the Computation of MDCT and IMDCT

18. High speed parallel architecture for cyclic convolution based on FNT

19. Design and Implementation of Wi-Fi MAC Transmit Protocol using VHDL

20. Design and Implementation of a 64-bit RISC Processor using VHDL

21. Implementation of a visible water marking in a secure still digital camera using VLSI design

22. Embedded a low area 32 bit AES for image encryption and decryption application

23. Design of AES (Advanced Encryption Standard) Encryption and Decryption)

24. 32-bit RISC CPU Based on MIPS

25. High Speed Hardware Implementation of 1D DCT/IDCT Efficient FPGA implementation of convolution

26. Implementation of a visible Watermarking in a secure still digital Camera using VLSI design

27. High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures

28. Implementation of FFT/IFFT Blocks for OFDM METHODOLOGIES

29. Design of 8-bit Microcontroller using verilog

30.

Design and Synthesis of High speed CAM using Xilinx Spartan3E

31. A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (Verilog)

32. Design and Implementation of Digital low power base band processor for RFID Tags (Verilog)

33. Design and Implementation of Reversible Watermarking for JPEG2000 Standard

34. FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging

35. Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (VHDL)

36. High Performance Complex Number Multiplier Using Booth-Wallace Algorithm

37. High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming

38. A HIGH PERFORMANCE VLSI FFT ARCHITECTURE

39.

Design of an Bus Bridge between OCP and AHB Protocol (VHDL)

40. Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter

41. Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block

42. Design of Data Encryption Standard (DES)

43. Design of Distributed Arithmetic FIR Filter

44. Design of Universal Asynchronous Receiver Transmitter (UART)

45. Design of Triple Data Encryption Standard (DES)

46. Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm

47. Design of Dual Elevator Controller

48. Design of an ATM (Automated Teller Machine) Controller

49. Design of 8-Bit Pico Processor

50. Design of JPEG Image compression standard

51. Design of Digital FM Receiver using PLL (Phase Locked Loop)