ARM CORTEXA9 FOR ALTERA SoC FPGA ONLINE TRAINING

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ARM CORTEX-A9 FOR ALTERA SoC FPGA For EMBEDDED SYSTEMS ONLINE TRAINING

TOPICS

Training materials
A carefully crafted combination of content from ARM, ALTERA and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
Fully indexed course notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge.
Content
ALTERA SoC FPGA architecure overview
Architecture details with Cortex-A9 MPCore implementation choices
Core and FPGA interfaces
Hard Processor System Built-in peripherals
Memories and memory controllers
FPGA logic and rooting details
I/O peripherals
Processor system boot options
Development and debugging software
Cortex-A9 core building blocks
Private peripherals
Snoop control unit
Accelerator coherency Port (ACP)
Generic interrupt controller
Core system interfaces

Introduction to ARM assembler programming
Load/Store Instructions
Data Processing Instructions
Data Processing Instructions
Flow Control
Miscellaneous
DSP

Caches
Cache basics
L1 and L2 Caches on ARM based SoCs
Caches configuration options
Optimization considerations

Exception Handlers for ARM application processors
Exceptions overview
Interrupts sources and priorities
Abort handlers
SVC handlers
Undef handlers
Reset handlers

Memory Management
Memory Management Introduction
Access Permissions and Types
Memory Management Unit (MMU)
Optimizations & Issues

Using the NEON co-processor
NEON instruction set overview
NEON software support

Writing C for ARM Processors
Parameter passing
Floating point linkage
Alignment
Coding considerations

Synchronization
Synchronization overview
Synchronization primitives
LDREX STREX applications

Embedded software development
An out-of-the-box build
Tailoring the C library to your target
Tailoring image memory map to your target
Reset and initialization
Further memory map considerations
Building and debugging your image

Software Engineers Guide to ALTERA SoC FPGA
Overview
Interconnect and interfaces
Level 1 memory system
Branch prediction

MPCore Logic
MPCore Features
Snoop Control Unit
Accelerator Coherency Port (ACP)
Interrupt Controller
Timer and watchdog
TrustZone Support
Developing for ARM MPCore Processors
Booting SMP
Configuring an interrupt
Synchronization

TrustZone
Exception handling
Memory system
Debug
Software

Appendix:

The AMBA AXI bus protocol
Protocol overview
Channels, transfers & transactions
Channel signal
Transfer behavior
Transaction ordering
AXI terminology.

Linker and Libraries Hints and Tips
Linking basics
System and user libraries
Veneers and interworking
Linker optimizations and diagnostics
ARM Supplied Libraries

Exercises:
DS-5/GNU toolchain introduction tutorial
Cover the use of command line and GUI tools to build and debug projects.
Assembler programming for ARM
Practice with the concepts covered in the ARM assembly module.
Exception handler programming
Studdy a complete system with vector table, exception handlers stubs and stacks setup.

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]