ARM CORTEXA9 For ZYNQ SYSTEM DESIGN ONLINE TRAINING

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ARM CORTEX-A9 For ZYNQ SYSTEM DESIGN For EMBEDDED SYSTEMS ONLINE TRAINING

ARM Cortex-A9 for Zynq System Design for Embedded Systems

TOPICS

Training materials
A carefully crafted combination of content from ARM, Xilinx and will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes:
Fully indexed course notes creating a complete reference manual

Associated Courses
Zynq System Architecture
Embedded Systems Hardware and Software Design
Advanced Embedded Systems Hardware and Software Design
Content
Day 1, am
Introduction to Zynq
Architecture details with Cortex-A9 MPCore implementation choices
Core and FPGA interfaces
Processing System Built-in Peripherals
Memories and Memory Controllers
FPGA logic and rooting details
I/O Peripherals
Processor System Boot Options
Cortex-A9 core building blocks
Private peripherals
Snoop control unit
Accelerator coherency Port (ACP)
Generic interrupt controller
Core system interfaces

Caches and Tightly Coupled Memories
Cache basics
Caches on ARM processors
Tightly Coupled Memory (TCM)
Optimization consideration

Day 1, pm
Introduction to ARM assembler programming (including Labs see below)
Load/Store Instructions
Data Processing Instructions
Flow Control
Miscellaneous
DSP

Day 2, am
Using the NEON co-processor
NEON Instruction Set Overview
NEON Software Support.

Exception Handlers for ARM application processors
Exceptions overview
Interrupts sources and priorities
Abort Handlers
SVC Handlers
Undef Handlers
Reset Handlers

Day 2, pm
Memory Management
Memory Management Introduction
Access Permissions and Types
Memory Protection Unit (MPU)
Memory Management Unit (MMU)
Optimizations & Issues

Synchronization Support
Synchronization primitives
SWP Instruction
LDREX / STREX and CLREX Instructions

Embedded software development
An out-of-the-box build
Tailoring the C library to your target
Tailoring image memory map to your target
Reset and Initialization
Further memory map considerations
Building and debugging your image.

Day 3, am
Software Engineer s Guide to Zynq
Zynq Peripherals
Cortex-A9 Pipeline
Media Processing Engine
Register Renaming
Fast Loop Mode
Program Flow Prediction
Preformance Monitoring Unit
Level One Memory System

Day 3, pm
MPCore Logic
MPCore Features
Snoop Control Unit
Accelerator Coherency Port (ACP)
Interrupt Controller
Timer and watchdog
TrustZone Support
Developing for ARM MPCore Processors
Booting SMP
Configuring an interrupt
Synchronization.

The AMBA AXI bus protocol
Protocoloverview
Channels, Transfers & Transactions
Channel Signal
Transfer Behavior
Transaction Ordering
AXI Terminology.

Appendix:
Introduction to TrustZone
Exception Handling
Memory System
Debug
Software

Compiler Hints and Tips
Basic Compilation
Compiler Optimizations
Coding Considerations
Local and Global Data Issues

Linker and Libraries
Linking Basics
System and User Libraries
Veneers and Interworking
Linker Optimizations and Diagnostics
ARM Supplied Libraries

Lab Exercises:
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.
Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by Xilinx as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.
Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]