COMPREHENSIVE SYSTEM VERILOG For EMBEDDED ONLINE TRAINING

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]

COMPREHENSIVE SYSTEM VERILOG For EMBEDDED SYSTEMS ONLINE TRAINING

Structure and Content

SystemVerilog for Designers (days 1-3)

SystemVerilog Basics

Introduction
What is SystemVerilog? Language Evolution SystemVerilog Language Features Caveats The UVM Family Tree Books and Resources

Verilog versus SystemVerilog
Logic Type Reg, Logic, and Bit Nets versus Variables - Refresh Wire versus Var

Programming Language Features
C-Like Language Features Static vs Automatic Variables Static vs Automatic Tasks ++, --, and Assignment Operators Labeling Time Units Do While Loop Immediate Assertions join_none and join_any Enhanced Tasks and Functions Task and Function Arguments Void Functions Argument and Return Types Type string $sformat and $sformatf

Bus-Functional Modeling
Simple Module-Based BFM Testbench using BFM Separate Test from Test Harness

Basic Data Types
4-state and 2-state Types Initial Values Caveats with Signed Types Enumerations Type-Checking of Enumerations struct typedef struct Packed Struct Packed and Unpacked Arrays Indexing Multidimensional Arrays Packages Packages and Ports

Interfaces
Simple Interface Package versus Interface Instantiating an Interface Accessing Interface Members Ports and Parameters on Interfaces Pin-Level Interface Modports Generic Interface Ports Task/Function in Interface Calling Task through Interface Port

SystemVerilog RTL

RTL Processes
SystemVerilog and RTL Synthesis Combinational Logic Clocked Processes always_comb, always_latch, always_ff Synthesis-Friendly If / Case priority case unique if unique case Wild Equality Operators case inside inside Operator

RTL Types
Synthesizable Data Types Enums for Finite State Machines Base Types and Values Rules for Overriding the Enum Values Packed Struct (Review) Packed Union Multidimensional Arrays Nets, Ports and Data Types Types and Packages Type Parameters Synthesis of Interfaces Multiple Drivers on a Bus How to Differentiate Connections? Modport Expressions Modport Expressions with Generate

SystemVerilog Assertions

The SVA Language
What are Properties? Property versus Assertion Benefits Of Assertions Who Writes Properties? Immediate and Concurrent Assertions Immediate Assertions Assertion Failure Severity Concurrent Assertions Temporal Behaviour Clocks and Default Clocks Holds and Implication Non-overlapped Implication Simulation of Assertions Assertion Coverage Simulation and Cover Property Binding

Properties, Assertions and Sequences
Implication Properties are checked on every clock |=> and |-> $rose() and $fell() $rose() vs posedge $past() $sampled() Properties using Expressions Named Properties Sequences Basic Syntax Concatenation Repetition Consecutive Repetition Unbounded Repetitions Zero Repetitions Non-Consecutive and Goto Repetition Sequence versus Implication $rose() and $fell() versus Sequence

More on Properties & Sequences (Optional Topic)
Sequence Operators Sequence Or Sequence and Non-Length-Matching and Sequence Length-Matching and Throughout Within first_match Property Operators Beware Negating Implications Operator Precedence Named Sequences and Properties Sequence Completion Variables and Procedures in Sequences Detecting the Endpoint of a Sequence Turning Assertions Off

Module-based SystemVerilog Verification

Clocking Blocks
Clocking Block Syntax Input and Output Skew Creating a Clocking Block Testbench and Clocking Block Cycle Delays and Clocking Input and Output Skew Syntax Summary Scheduler Regions Stimulus and Response Signal Aliasing Multiple Clocking Blocks Driving a Net Clocking Blocks in Interfaces Clocking Blocks versus Programs

Randomization
Constrained Random Verification Random Numbers in SystemVerilog std::randomize Constraint Syntax Seeding and Random Stability Saving & Restoring Seeds Random Sequence of Valid Actions Randcase Randsequence

Coverage
Functional Coverage Coverage Bins Further Options Transition Coverage Cross Coverage Adjusting Stimulus Using Coverage

Arrays and Queues
Dynamic Arrays Queues Working with Queues Queue Methods Nesting, Assignment Patterns, and %p Array-like Containers Associative Arrays Associative Array Methods Foreach

Other Language Features (Optional Topic)
$root and $unit Enumeration Methods Arrays for Multidimensional Structures Initializing an Unpacked Array Replication in an Assignment Pattern Packed Arrays and Structures Pass-by-Copy Pass-by-Reference const ref Array Querying Functions $bits Bit-stream Casting Array Manipulation Methods Array Locator Methods Array Ordering Methods Array Reduction Methods Other IEEE 1800-2009 Features

The Direct Programming Interface (Optional Topic)
DPI Simulation Flow Command-line Switches Importing a C Function Changing the Imported Function Name Mapping Data Types of Arguments Exporting a Function to C Sandwiches and Transparency Importing and Exporting Tasks Scalar Bit and Logic Arguments Packed Arrays Decoding the Canonical Representation String Arguments Open Array Arguments Task Return Values Task Disable Flow Pure and Context

Class-based SystemVerilog Verification (days 4-5)

Classes for Transactions
Constrained Random Verification Representing Transaction Data SystemVerilog Classes Object = Instance of Class Constructor Constructor Arguments

Class Members and Copying
Static Data Members Constant Data Members Randomized Data Members Data Members of Class Type Forward Typedef Object Copy with new Shallow Copy Deep or Shallow Copy?

Virtual Interfaces
Test Harness and Testbench Modules versus Classes Creating the Testbench Virtual Interface Building a test harness Adding a clocking block Connecting the virtual interface Accessing a Task through a Modport Testbench Static Structure BFM or Driver Class Testbench Object Structure

Extending Classes for Stimulus
Improved Generator Class Constrained randomization Creating an Extended Class The Inheritance Relationship Inheriting Class Members Control Knobs and Constraints Methods of Extended Class Derived-class Object, Base-class Variable Virtual Methods General-Purpose Infrastructure

TLM and Channels
Reusable Verification Environments Transaction Level Modeling Using Channels Generic Channel and Transaction Classes Out-of-Block Declarations Connecting Channels Getting Data from a Generic Channel Safe Downcasting with $cast Type Parameterization of Classes Running Components with fork...join fork...join_none Identifying Forked Processes

Component Hierarchy
Testbench Component Hierarchy Implementing Relationships Base Classes (review) Abstract Class and Pure Virtual Methods Interface Classes in IEEE 1800-2012 Component Base Class Launching a Task with fork...join_none Customising a Component Constructing a Component

Monitors and Checkers
Kinds of BFM-Like Component Monitors and Checkers Bus Protocol Checking Modports for Driver and Monitor Monitor Implementation Using the Monitored Transactions Checker Implementation Mutual Exclusion Semaphore Class Checker with Mutual Exclusion

Functional Coverage
Coverage Driven Verification Verification Planning From Features to Tests Covergroups Embedded Covergroups Procedural Sampling Arguments and Options Coverage Bins Bins and Coverage Cross Coverage Cross Coverage and Labels Cross Coverage Example Controlling Cross Bins

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]