EXPERT VHDL For EMBEDDED SYSTEMS ONLINE TRAINING

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EXPERT VHDL For EMBEDDED SYSTEMS ONLINE TRAINING

TOPICS

Training materials
Training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Class fees include:
Fully indexed class notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge
Golden Reference Guide for language, syntax, semantics and tips
Tour guides (to support the tools and technologies of your choice).

Structure and Content
Expert VHDL Design (Days 1-2)

RTL Synthesis and Synchronisation
Synchronous Design Synthesis of combinational and sequential logic Variables in clocked processes How Many Registers? Synchronous Design Rules Static Timing Analysis Non-Synchronous Features Timing Analysis Exceptions Asynchronous Inputs Input Hazard Metastability Synchroniser in VHDL Multiple Clock Domains Transferring Data Between Clock Domains Using a FIFO for Synchronisation Controlling a Flag from Two Clock Domains Clock Divider in VHDL Clock Divider Timing Synchronising Reset Re-timing and Pipelining Hierarchy and Optimisation REGISTERED Ports

Introduction to VHDL 2008 (Design)
Status of VHDL 2008 Overview of VHDL 2008 Convenience Features Example (Design) Changes to port maps Major Changes in VHDL 2008 New Packages Extended Generics Generics on a Package Type Generics Subprogram generics VHDL 2008 Operators VHDL 2008 Types Statements

Writing Readable Designs
VHDL Features for Abstraction Record Types Using Record Fields Aggregates Using Records for Wiring Connecting Records Inside a Peripheral Multiplexed Bus Structure Multiplexing Records RepresentingREGISTER Maps Accessing Individual Registers Accessing the StatusREGISTER Collecting Registers Together Alias Using Aliases with Vectors Using Alias with a Bus Other Uses of Alias Named Ranges

Writing for Synthesis
Using NUMERIC_STD Numeric_std and Std_logic_vector Conversions Summary of NUMERIC_STD Arithmetic WYSIWYG Eliminating the Mux Forcing an Implementation Inference or Instantiation? Synthesis Attributes How Clever is Your Synthesis Tool? Resource Sharing Eliminating Loop Dependencies Multiple Drivers Tri-state Inference Clocked Tri-states Dynamic Indexing Handling Unknowns Don t Cares STD_MATCH One-Hot Decoding

Writing For Re-Use
Re-use Tradeoffs A Universal Re-use Methodology? Language-Level Re-use Reusing Code Fragments Standard Component Re-use IP Deliverables Writing Re-usable RTL IP Example of a Regular Structure Regular Ports Types and Subtypes Using Generics Parameterised Ports Array Attributes Parameterising Ranges Unconstrained Array Ports Regular Implementation Structure Using Generate Parameterised Regular Implementation Generate or Loop? Generating Instances Generating Attribute Values Regular Output Logic Parameterised Output Logic More Multiple Driver Issues Longest Static Prefix Optional Ports Default On Component Component Libraries

Advanced Coding Styles
Subprograms Procedures Destructive Register Reads Read Procedure Functions Subprograms in Packages Recursion Recursive Function Example Creating a Generic Counter Recursive Instantiation Recursive Component Declaration Solving the Problem Recursion Synthesis Results Arrays of Arrays Multidimensional Arrays Flattening Matrices Re-use Revisited Multidimensional Arrays of Ports Getting and Setting Rows Architecture Using 2D Arrays Instancing The Design

Finite State Machine Synthesis
State Transition Diagrams Finite State Machines Two Process State Machine in VHDL Timing in a Synchronous Design One Process State Machine Description State Machine Architecture Comparison of Coding Styles Separate Output Decoding EasierREGISTERED Outputs Registered Outputs Using Local Variables State Encoding Unreachable States Controlling Unreachable States No Output Decoding Explicit One Hot Style Hand Optimised One Hot Style Collision Signal Too Many States?

Expert VHDL Verification (Days 3-5)

Functional Verification
What Is Verification? Approaches to Verification Verification Strategy What to Verify? Towards a Verification Plan Don t Plan Everything Identify Testcases Verification Metrics Coverage Including Functional Coverage Coverage Driven Verification From Features to Tests Checking Verification Planning Revisited The Basic Testbench Verification Environment Verification Methodologies VHDL Methodology Verification Resources Design for Verification Glass Box Testing Analysis to Choose Tests Boundary Conditions & Corner Cases Analysis to Choose Tests Black Box Testing Regression Testing Stress Testing Different Sorts of Stimulus Random Stimulus Constraining Random Stimulus Random Sequence of Valid Actions Checking Results

Subprograms
Using Abstraction in a Testbench Procedures Parameter Class, Mode, and Type Functions Subprograms in Packages Signal Parameters Subprogram Overloading What is a (VHDL) Transaction? Wait Statements and Time

Vector Based Testing
The Basic Testbench TEXTIO Output Opening and Closing Files TEXTIO Input Testing the File Open Status Managing Text Files Procedure READ When READ Goes Wrong Package STD_LOGIC_TEXTIO Converting Values to Text Strings Checking Expected Results Using Built-in Files Reading Variable Length Data Files Without Textio Binary Files Testbench Start Stopping A Testbench

Comparing Models
Comparing Results Configuration Default Configuration Hierarchical Configurations Nested Configurations Checking RTL Vs. Gate Level Sampling Data RTL Postponed Processes Sampling Data Gate Level Interfacing Design Entities Type Conversions Strength Strippers VHDL Netlist Simulating the Netlist VHDL Configuration Using a Signature Register Signature Analysis Signature Analysis Improvements

Time In Testbenches
Inspecting the Event Queue Example SRAM Timing Setup Time Check Hold Time Check Combined Setup / Hold Time Check Pulse Width Check 0 to 1 Change Entity Declarations Passive Processes Using Vital Packages Setup/Hold Check With Vital What About Transactions? Concurrent Signal Assignments Drivers How to See Drivers Sequential Signal Assignments Inertial Delay Identical Successive Assignments Transport Delays

Coping With Latency
Variable Latency Record Types User Defined Array Types Arrays of Records Queues VHDL Queue Implementation Using Queues Coping with Out-of-Order Completion Scoreboarding Shared Variables Impure functions Protected types Protected type body Declaring a Shared Variable

Properties and Assertions
Property versus Assertion Applying Properties Who Writes Properties? Observability A Simple Assertion Simulation Checker or Monitor Properties and the Specification OVL Using OVL with VHDL OVL Packages OVL Configuration Instancing an Assertion OVL VHDL Assertions Example Assertions PSL The Elements of a Property PSL Basics The Structure of PSL The Boolean Layer Clocks and Default Clocks Holds and Implication next The Temporal Layer The Verification Layer Verification Units Modelling Layer Using PSL with an HDL Simulation of Temporal Properties Summary of Benefits

Modelling Techniques
Modelling Components Behavioural Modelling Example Modelling the 2-wire Bus Model Structure Two Wire Slave Model Protocol Implementation Data Generation Slave Procedure Modelling State A/D and D/A Models Sampled Analogue Circuits Dynamic Memory Allocation Access Types Allocators Deallocating Memory Writing to a FIFO Reading from a FIFO Pointer Problems

Transaction Level Verification
Structuring Testbenches Transaction Level Testcase Making a Transaction in VHDL Communicating Transactions A Simple Example Generating Transactions Using Procedures with Signals A Systematic Approach Non-blocking Procedures Bus Functional Modelling Interfacing Without Events Bus Functional Model Bus Functional Model Using get Synchronization Synchronization Channel Synchronization Channel Details

Testbench Architecture
Verification Reminder Completing our Methodology Monitoring Internal Signals The Objection Mechanism Implementing Objection Run-time Configuration Path Name Implementing Run-time Configuration Functional Coverage Coverage Using Concurrent Procedures Coverage Procedure Calling Coverage Procedures Why Use Path Parameter? Verification Recommendations Package Useful Functionality Build the Complete Testbench Monolithic Testbenches are Inflexible Hide DUT Interface from Testcase Layered Architecture Interface Between Layers Separate Top-Level Entities Creating Multiple Instances

Appendix Co-simulation
Embedded Systems Logic Simulation Instruction Set Simulation (ISS) Native Compiled Software Co-simulation Tools Simulating Software Execution Modelling Memory Systems Synchronisation Requirements for ISS Hardware/Software Co-simulation Benefits Foreign Language Interfacing Requirements of a FLI FLI Implementation Interfacing to a C program Foreign Architecture Foreign Subprograms Foreign Architecture Example VHPI Example VHPI Callback VHPI Elaboration Code

Appendix Advanced VHDL Language
Run-time Configuration Example User API Protected Type Declaration Deferred Constants Protected Type Body getConfigInfo Helper Function Text Processing Protected Type Method Avoiding Protected Types Modified tbpack A further simplification

Appendix Introduction to VHDL 2008 (Verification)
Status of VHDL 2008 Overview of VHDL 2008 Convenience Features Example (Design) Example (Verification) Improved IO Changes to port maps Major Changes in VHDL 2008 New Packages Extended Generics Generics on a Package Type Generics Subprogram generics VHDL 2008 Operators VHDL 2008 Types Statements.

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]