SYSTEM VERILOG TRAINING IN HYDERABAD

ADVANCE DIPOLMA COURSE IN ASIC DESIGN & VERIFICATION

ADVANCE DIGITAL ELECTRONICS

Introduction to VLSI
ASIC Design Flow
Logic Gates
Number Systems and Code Conversions
K-maps
Combinational Logic Circuits
Sequential Logic Circuits
Flip-Flops
Counters
Registers
Finite State Machine
Memory Organizations
Programmable Logic Devices (FPGA s)

LINUX

Introduction to Linux OS
Basics of Linux commands
Basics of Shell scripting
Basics of Perl scripting

VERILOG HDL

Introduction to Verilog HDL
Modeling Concepts
Gate Level Modeling
Data Flow Modeling
Behavioural Modeling
Structural Modeling
Switch Level Modeling
Data Types
Operators
Procedure and Flow Of Control Statement
Designing of Combinational Circuits
Designing of Sequential Circuits
FSM Design Modeling
Designing of Memories
Writing Testbench using Verilog
Task and Functions
System Tasks
Compiler Directives
Advance Nets in Verilog
Bus Functional Modeling
Verilog Based Assertions
Code Coverage.

SYSTEM VERILOG

Introduction to Verification Plan
Introduction to System Verilog
Data types
Procedural & Flow Control Statements
Arrays
Task And Functions
Interfaces and Clocking Block
Program Blocks
Fork Join Statements
OOPS Concepts
Randomization and Constraints
Mailboxes Semaphores
Events
Virtual Interfaces
Assertions
Functional Coverage
Packages
Writing Testbench in System Verilog
Project supported based on Methodology
Methodology : UVM
EDA TOOLS

QuestaSim
Modelsim
Xilinx ISE