THE LATEST METHODOLOGIES For DESIGN VERIFICATION

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]

THE LATEST METHODOLOGIES For DESIGN VERIFICATION For EMBEDDED SYSTEMS ONLINE TRAINING

Course materials
Course fees include fully indexed course notes providing you with a complete reference manual.
A Workbook with all lab exercises and example solutions is included.
The source code for the lab exercises will also be provided.

Structure & Content
Introduction
Motivation Cost of Bugs Terminology The Design Process The Verification Process Observability Controllability Verification Levels

Verification Planning
Importance of Planning Specifications Feature Extraction Identifying Corner Cases Targets and Metrics Unit and System-Level Verification Planning

Directed Testing
Verification Tools and Languages Basics of Testbenches Driving and Checking Limitations

When is verification done?
Sign-off Criteria Comprehensive Code Coverage Functional Coverage Combining Coverage Models The Coverage Closure Challenge Regressions Verification Management

Constrained Random Generation
Motivation Coverage with a focus on Functional Coverage Testbench Automation Modern Testbench Structure Transactors Coverage-driven Verification

Advanced Checking
How to predict expected results Advanced Checkers Reference Models Self-checking Testbenches Monitors Scoreboards Coherency

Assertion-Based Verification
Terminology Use Temporal Properties Property Formalization Simulation with Assertions Observability Assertion Coverage Property Re-use

System-Level Verification
Architecture of the top-level Testbench Top-Level Testing Controllability and Observability Advanced Constrained Random Techniques Configurations Warm Loading System-Level Properties and Assertions System-Level Debug Coverage above Unit Level Power-Aware Verification Accelleration Validation Performance Verification Quality of Service

Verification Flow
Specification Plan Verification Environment Debug Regression Escape Analysis Re-use Advanced Verification Methodologies Verification Review

Foundations of Formal Verification
Motivation Terminology Formal Property Checking Developing Properties Safety, Liveness and Invariant Properties Environment and Assumptions Interpreting the Outcome of Formal Property Checking Coverage Benefits and Strengths of Formal Verification

Advanced Formal Verification
Bug Hunting Bug Absence Bug Analysis Checking Bug Fixes Coverage Closure X-Propagation Advanced Property Specification and Capture Strategies for Coping with Complexity Bounded Proof Bug Avoidance Finding Invariants Property Re-use and libraries

For more details Please contact LEARNCHASE
www.learnchase.com
Whatsapp: +918123930940
E-mail Id: [email protected]
E-mail id: [email protected]