6 weeks training for B-tech students in VHDL

VHDL, a VHSIC (very high speed integrated circuit) is a hardware description language which is used to describe digital signal systems such as integrated circuits, and is used in electronic design automation. They are a very important sub domain of VLSI, and forms the part of front end.

Some of the basic features of this language are:
Used to define behavior and structure of digital hardware electronic system.
Used for conventional digital circuits as well.
Defined by Language Reference Manual (LRM).
VHDL is an international standard language regulated by IEEE.
The two main kinds of tool that operate on VHDL language are simulation and synthesis. It allows design to be represented in any method- such as top to bottom, from middle etc.