EC/EE B-tech students in VLSI

System Verilog is the combination of Hardware Description Language (such as VHDL and Verilog) and Hardware Verification Language together with some feature from C/C++ The application of System Verilog is used in semiconductor and electronics design industry for the purpose of verification.
Some of the basic features of this language are:
It is used for verification of all digital ICs..
It has feature inherited from Verilog HDL, VHDL, C/C++.
It is open source software which can be used by any company.
It handles all types of design and verification flow such as design description, functional stimulation, property specification and formal verification.
System Verilog is a superset of Verilog. It supports all the features of Verilog and added features of OOPS as well. Hence it’s a super Verilog.

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