VLSI 6 Weeks Summer Training

Verilog is a Hardware Description Language which is used to model complex electronic components. It is standardized as IEEE 1364.It is commonly used for two purposes. They are
Design
Verification of digital circuits
It is basically used for verification of analog circuits and mixed-signal systems. Verilog as Hardware Description Language includes signal strengths and considers way of describing the propagation time which differentiates it from the software programming language. Verilog HDL is easier to learn as compared to VHDL due to emphasis on C language.

Verilog HDL is also case sensitive and is not strongly typed. It has very simple data types but lacks the library management as compared to VHDL. It is a very important sub domain of VLSI and forms part of front end.

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