| Course Teaching | You are Offering Professional Course | Locality Bajaj Nagar |
VLSI
Introduction to VLSI
Evolution of VLSI Systems
Applications of VLSI Systems
Processor Based Systems
Embedded Systems
FPGA Based Systems
Digital System Design Using FPGAs
Spartan-3 FPGAs
Introduction to VHDL language
Digital Electronics
Introduction to Digital Electronics
Number systems
Code conversions
Arithmetic s
Boolean algebra
Logic gates
Combinational logic design
Standard representation of logical functions
Karnaugh map method
MSI circuits
Multiplexers/demultiplexers
Adders / subtractors
Arithmetic Logic Unit (ALU)
Encoders/ Decoders
Flip Flops
Flip-flops
Type of Flip flops
Conversion of flip flops
Application of flip flops
Sequentional circuit design
Registers
Types of shift registers
Application of registers
Counters
Ripple or Asynchronous counters
Synchronous counters
Clocked sequential circuits
Designing of Memories
Introduction
Memory Organization and operation
Expanding memory size
Expanding memory capacity
Different types of memories
Programmable Logic devices
Introduction
Programmable logic array (PLAs)
Programmable array logic (PALs)
Complex programmable logic devices (CPLDs)
Field programmable gate array (FPGA)
Computer-Aided Design Tools (CAD)
Circuit Design with VHDL
Introduction to VHDL
Code structure
Library Functions
Entity
Architecture
Configuration Declaration
Package Declaration
Elements of VHDL LANGUAGES
Different Data types
Operators
Attributes
Generic
Identifiers
Variables & Signals
Different types of VHDL Modeling
Behavioral modeling
Modeling techniques
If statement
Case statement
Wait statement
Loop statement
Process statement
Dataflow modeling
When statements.
Block statement
Generate statement
Structural Modeling
Component declaration
Component instantiation
Test Bench
Modeling a Test Bench
Test Bench for Combinational Circuits
Test Bench for Sequential Circuits
Design and synthesis by using Verilog HDL
Introduction to Verilog HDL
Evolution of CAD
Typical Design flow
Importance of HDL's
Popularity of Verilog HDL
Modeling Concepts
Design methodologies
Module concept
types of modeling
Basic Concepts
Lexical Conventions
Number Specifications
Strings
Data Types
System Task
Compiler Directives
Modules
List of Ports
Port Declaration
Port Connection Pins
Gate Level Modeling
Different Types of Gates
Gate Delays
Data Flow modeling
Continous Assignments
Delays
Epression Operators
Operators Types
Behavioural Modeling
Structured Procedures
Intial Statement
Always Statement
Event- Base Timing Control
Conditional Statements
If Statements
Case Statements
Loop Statements
Task and Functions
Different between Task and Function
Function
Task
Switch Level Modeling(optional)
Labs
Introduction to XILINX tools
Entering HDL code
Synthesis and implementation
Creating Test Bench
Simulation
Physical Realization
ABOUT PROJECT:
Project Basics, Module Explanation
Presentation basics
Report preparation guide lines
PRESENTATION:
Introduction to Project
Block Diagram
Scope of work
Schematic Diagram and Explanation
Software Flow chart
Tools used
Applications
Advantages and Limitations
Simulation results
Conclusion
Courses Offered:
EMBEDDED SYSTEMS
MATLAB
VLSI DESIGN
PLC,SCADA,DCS,VFD S
LINUX DEVICE DRIVERS
JAVA
DOTNET
iPHONE
AUTOCAD,CATIA,ANSYS
PHP SAP
ROBOTICS
Address :
Nano Scientific Research center
#S10,opp to LIT college,
Bharath Nagar
Nagpur