MTech Projects on VLSI Design

VLSI stands for Very Large Scale Integration. ... Projects in VLSI-based system design are the projects which involve the design of various types of digital systems that can be implemented on a PLD device like an FPGA or a CPLD. The projects which deal with the semiconductor design are called Projects in VLSI design.

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Shadow: A Lightweight Block Cipher for IoT Nodes
The advancement of the Internet of Things (IoT) has promoted the rapid development of low-power and multifunctional sensors. However, it is seriously significant to ensure the security of data transmission of these nodes.
Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis
The DS2B has the advantages of simple structure and good encryption performance. A different number of strong S-boxes could be generated with minor variations in the DS2B parameters. Performance analyses of the DS2B, including differential/linear cryptanalysis, bijective, nonlinearity, strict avalanche criterion (SAC), and bit independence criterion (BIC) have been presented where high and low differential uniformity is achieved. Besides, a comparison with recent S-boxes is introduced which shows the robustness of the DS2B.
Design Optimization for Low-Complexity FPGA Implementation of Symbol-Level Multiuser Precoding
Low-complexity FPGA design for symbol-level precoding (SLP) in multiuser multiple-input single-output (MISO) downlink communication systems. In the optimal case, the symbol-level precoded transmit signal is obtained as the solution to an optimization problem tailored for a given set of users' data symbols.
Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal
Low-complexity, high-speed, and reconfigurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of the acquired seismic signals in a real-time seismic-alert system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (Los) and logic depths (LDs) in the digital FIR filter.
High-Speed and Area-Efficient Scalable N-bit Digital Comparator
An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bit widths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure.
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