vlsi projects using verilog

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1. A CMOS PWM Transceiver Using Self-Referenced Edge Detection
2. Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model
3. High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis
4. High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors
5. On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ
6. Read Performance The Newest Barrier in Scaled STT-RAM
7. An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells
8. A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique
9. A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links
10. A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology
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