vlsi training in nano scientific research centre

www.nsrcnano.com, www.nanocdac.com, #604, 601 Siri Estates, Opp. Lane to R.S. Brothers, Ameerpet, Hyderabad-500016. Ph: 040-23754144
E-mail: [email protected], www.nsrcnano.com, www.nanocdac.com An ISO: 9001:2008 Certified Company
ADVANCE DIPOLMA COURSE IN ASIC DESIGN & VERIFICATION
ADVANCE DIGITAL ELECTRONICS
? Introduction to VLSI
? ASIC Design Flow
? Logic Gates
? Number Systems and Code Conversions
? K-maps
? Combinational Logic Circuits
LINUX
? Introduction to Linux OS
? Basics of Linux commands
VERILOG HDL
? Introduction to Verilog HDL
? Modeling Concepts
? Gate Level Modeling
? Data Flow Modeling
? Behavioural Modeling
? Structural Modeling
? Switch Level Modeling
? Data Types
? Operators
? Procedure and Flow Of Control Statement
SYSTEM VERILOG
? Introduction to Verification Plan
? Introduction to System Verilog
? Data types
? Procedural & Flow Control Statements
? Sequential Logic Circuits
? Flip-Flops
? Counters
? Registers
? Finite State Machine
? Memory Organizations
? Programmable Logic Devices (
? Basics of Shell scripting
? Basics of Perl scripting
? Designing of Combinational Circuits
? Designing of Sequential Circuits
? FSM Design Modeling
? Designing of Memories
? Writing Testbench using Verilog
? Task and Functions
? System Tasks
? Compiler Directives
? Advance Nets in Verilog
? Bus Functional Modeling
? Verilog Based Assertions
? Code Coverage.
? Semaphores
? Events
? Virtual Interfaces
? Assertions
? Arrays
? Task And Functions
? Interfaces and Clocking Block
? Program Blocks
? Fork Join Statements
? OOPS Concepts
? Randomization and Constraints
? Mailboxes
PHYSICAL DESIGN
? Trends And Challenges In VLSI
? ASIC Flow
? Introduction of Transistors
? Introduction of CMOS Technology
? Stick Diagrams
? Lambda Rules
? Layouts
An ISO: 9001:2008 Certified Company
STA (
? Setup/Hold Time definitions & Slack Calculations.
? Different Timing Path Analysis.
? Analysis & approach to minimize the timing violations.
? STA Constraint development.
PLACE & ROUTE
? Floor Planning
? I/O Ring & Power Grid Planning
? Placement Methodologies
? CTS
DFT (
? ATPG Algorithms
? Functional Coverage
? Packages
? Writing Testbench in System Verilog
? Project supported based on Methodology
Introduction to Methodology UVM
EDA TOOLS
? QuestaSim
? Modelsim
? Xilinx ISE
? At-Speed Testing
? IDDQ Testing & Memory BIST
? I/O Testing
? Pattern Generation
ARCHITECTURE
? SOC Bus Structure
? SOC Processor Architecture
? SOC peripherals
LOGIC DESIGN
? FSM Design & FIFO Design
? Handshaking Protocol s
? Math Function Implementation
? Reset Design
? Clock Management
EDA TOOLS
? Micro Wind Layout
? DSCH Schematics
? H-Spice & Spice Language(